Authors - Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Misaki Takagi, Yujie Zhao, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
Abstract - This paper describes a 12bit, 1ps resolution, 5ns full-scale time-to-digital converter (TDC) for LSI test system application. The TDC is realized with discrete electronic components on a board for low cost, which is suitable for LSI test system application and expected to use as built-in self-test circuit (BOST). In the TDC, the upper 9 bits are obtained by successive approximation register (SAR) configuration using 9-bit programmable variable delay elements, while the lower 3 bits are by injecting jitter at the TDC input, measuring 100 times and estimating the most probable digital value with the statistical processing. The prototype TDC performance is evaluated with experiments.